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    by Published on 09-01-2014 02:00 PM
    1. Categories:
    2. Semiconductor Design
    content/attachments/11905-weaknode1.jpg

    Most analog cells have a power off mode intended to reduce power consumption. In this mode, all the circuit branches between the supply lines are set in a high impedance mode by driving MOS gates to a blocking voltage. This is a somewhat similar situation to that in tri-state digital circuits.

    When ...
    by Published on 09-01-2014 07:00 AM
    content/attachments/11962-ppt-slides-like-children.jpg

    The nice thing about webinars is that if you register for the live one and you can't attend you will still get first notice when the replay goes up. The other nice thing is that you can read a blog review of a webinar or whitepaper on SemiWiki first to see if it is worth your time. If you do attend ...
    by Published on 09-01-2014 01:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Mentor,
    4. Mentor Functional Verification
    content/attachments/11926-seq_req.jpg

    Often in an UVM agent, a sequencer is considered just to initiate stimulus on an interface, but an in-depth study of its behavior reveals that it can be modelled in multiple other ways; for example, as a responder to traffic from DUT. In UVM, the functionality of sequencers can be encapsulated ...
    by Published on 08-31-2014 11:30 AM
    1. Categories:
    2. Semiconductor Design,
    3. Silvaco
    content/attachments/11954-periodic-table.jpg

    The periodic table shows that Silicon (Si) is in a column along with other elements like Carbon (C) and Germanium (Ge). With so much emphasis on Silicon, you'd think that the other semiconductor materials have been neglected a bit.



    Silicon is a wonderful material and most of our consumer electronics and handheld devices use this ...
    by Published on 08-31-2014 05:01 AM
    1. Categories:
    2. Semiconductor Services,
    3. eSilicon
    content/attachments/11961-sm_logo.jpg

    Next week, eSilicon are kicking off a very widespread survey to measure some important semiconductor design and manufacturing challenges. Their goal is to measure customer sentiment regarding how Big Data, the Cloud and the Internet can impact these challenges. But here's a secret, the survey ...
    by Published on 08-30-2014 05:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Cliosoft
    content/attachments/11943-world-map3.jpg

    In the face of shrinking time-to-market windows, semiconductor companies are aggressively vying with each other to emerge with new or variants of existing ICs and SoCs to gain market share. The growth of the mobile market –wireless, networking, ...
    by Published on 08-29-2014 02:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. MunEDA
    content/attachments/11854-fpga-routing-architecture.jpg

    RTL designers know that their code gets transformed into gates and cells by using a logic synthesis tool, however these gates and cells are further comprised of transistors and sometimes you really need to optimize the transistor sizing to reach power, performance and area goals. I've done transistor-level IC design before, and the old process of manually choosing a transistor size, simulating in SPICE, analyzing, then changing the transistor size to re-iterate is a time consuming process. ...
    by Published on 08-29-2014 05:01 AM
    1. Categories:
    2. Semiconductor Design,
    3. Mentor Simulation
    content/attachments/11932-systemvision.jpg

    Next week Mike Jensen of Mentor will present a webinar Improving Complex System Design Reliability and Robustness. The webinar will be presented live twice and presumably available for replay soon after, as is usually the case:

    • September 4th 6.00-6.45am pacific
    ...
    by Published on 08-28-2014 02:00 PM
    1. Categories:
    2. Semiconductor IP,
    3. FPGA,
    4. Arteris
    content/attachments/11912-altera-arria-10-mpsoc-system-interconnect.jpg

    Advantages to using NoCs in SoC design are well documented: reduced routing congestion, better performance than crossbars, improved optimization and reuse of IP, strategies for system power management, and so on. What happens when NoCs move into FPGAs, or more accurately the SoC variant combining ARM cores with ...
    by Published on 08-28-2014 05:01 AM
    1. Categories:
    2. Semiconductor Manufacturers,
    3. TSMC
    content/attachments/11920-tsmc3.jpg

    For several years now, TSMC has run increasingly sophisticated IP validation. Ramping a new process as a foundry requires a number of things to all come together almost simultaneously: the process, of course, and some designs to run and start to ...

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