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    by Published on 07-28-2014 06:01 AM
    1. Categories:
    2. Semiconductor Manufacturers,
    3. STMicroelectronics
    content/attachments/11635-sfdsoi2.jpg

    There has been a lot of controversy about whether FD-SOI is or is not cheaper to manufacture than FinFET. Since right now FinFET is a 16nm process (22nm for Intel) and FD-SOI is, for now, a 28nm process it is not entirely clear how useful a comparison this is. Scotten Jones has very detailed process ...
    by Published on 07-27-2014 06:00 PM
    1. Categories:
    2. Semiconductor IP
    content/attachments/11664-semiconductor-ip-soc.jpg

    Royalty is a critical component in any IP deal. SoC companies want IP companies to share the risk of success (or failure) of their SoC and to enable that they want IP vendors to accept a substantial part of their payment to be paid as royalty. But the customers are also not very interested to shell out huge money ...
    by Published on 07-27-2014 08:10 AM
    1. Categories:
    2. FPGA,
    3. Xilinx
    content/attachments/11662-altr-vs-xlnx.jpg

    One of the things I do in my spare time is listen to quarterly conference calls and try to sort fact from fiction. I compare past calls to the current one and attempt to predict what’s coming next. Confucius said, “Study the past if you would define the future” and I’m a big believer in that.

    Paul McLellan wrote about the Xilinx call earlier this week:
    Xilinx:
    ...
    by Published on 07-26-2014 06:00 PM
    1. Categories:
    2. Semiconductor Services,
    3. eSilicon
    content/attachments/11667-esilicon-gdsii-interface.jpg

    On Thursday, July 31st at 8 AM Pacific Daylight Time I’ll be moderating a webinar that will demo eSilicon’s new GDSII quoting portal. You can find more details about the webinar here, and you can register ...
    by Published on 07-26-2014 06:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Coventor
    content/attachments/11659-sram-halfcell.jpg

    We all know that Technology Computer Aided Design (TCAD) simulations are essential in developing processes for semiconductor manufacturing. From the very nature of these simulations (involving physical structure and corresponding electrical characteristics ...
    by Published on 07-25-2014 12:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Mentor,
    4. Mentor Simulation
    content/attachments/11649-pkg_pd_flow.jpg

    In my career in semiconductor industry, I can recall, in the beginning there was emphasis on design completion with automation as fast as possible. The primary considerations were area and speed of completion of a semiconductor design. Today, with unprecedented increase in multiple functions on the same chip ...
    by Published on 07-25-2014 07:01 AM
    1. Categories:
    2. Semiconductor Design,
    3. Synopsys
    content/attachments/11597-he0.jpg

    Hybrid emulation is when part of the system is run in the emulator and part of the system is run in a virtual prototype. Typically a model of the processor(s) is run in the virtual platform and then the rest of the design is modeled by running the RTL on the emulator. I ...
    by Published on 07-24-2014 10:00 PM
    1. Categories:
    2. Semiconductor IP,
    3. CEVA
    content/attachments/11655-ceva-soc-platform-ip.jpg

    Processor and GPU cores usually get the limelight, driven by the ARM and Imagination machines occupying the center square of most SoC designs. CEVA has quietly been assembling DSP IP in most of the squares around the edge, and may have just reached critical mass for wearables and IoT devices. ...
    by Published on 07-24-2014 02:00 PM
    1. Categories:
    2. General
    content/attachments/11648-skybell.jpg

    Paul McLellan and I spent the evening with Samsung at the Bentley Reserve in San Francisco last night. One thing I discussed with them in great detail was IoT devices. Samsung is investing heavily in IoT and the supporting infrastructure. ...
    by Published on 07-24-2014 09:05 AM
    1. Categories:
    2. Semiconductor Design,
    3. Docea Power
    content/attachments/11627-memory-hierarchy.jpg

    One great benefit of designing at the ESL level is the promise of power savings on the order of 40% to 70% compared to using an RTL approach. Since a typical SoC can contain a hierarchy of memory, this kind of power savings could be a critical factor in meeting PPA goals. To find out how an SoC designer could use such an ESL approach to power savings for a system memory subsystem I interviewed Gene Matter of DOCEA Power by email this week. DOCEA's company headquarters ...

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