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    by Published on 08-29-2014 02:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. MunEDA
    content/attachments/11854-fpga-routing-architecture.jpg

    RTL designers know that their code gets transformed into gates and cells by using a logic synthesis tool, however these gates and cells are further comprised of transistors and sometimes you really need to optimize the transistor sizing to reach power, performance and area goals. I've done transistor-level IC design before, and the old process of manually choosing a transistor size, simulating in SPICE, analyzing, then changing the transistor size to re-iterate is a time consuming process. ...
    by Published on 08-29-2014 05:01 AM
    1. Categories:
    2. Semiconductor Design,
    3. Mentor Simulation
    content/attachments/11932-systemvision.jpg

    Next week Mike Jensen of Mentor will present a webinar Improving Complex System Design Reliability and Robustness. The webinar will be presented live twice and presumably available for replay soon after, as is usually the case:

    • September 4th 6.00-6.45am pacific
    ...
    by Published on 08-28-2014 02:00 PM
    1. Categories:
    2. Semiconductor IP,
    3. FPGA,
    4. Arteris
    content/attachments/11912-altera-arria-10-mpsoc-system-interconnect.jpg

    Advantages to using NoCs in SoC design are well documented: reduced routing congestion, better performance than crossbars, improved optimization and reuse of IP, strategies for system power management, and so on. What happens when NoCs move into FPGAs, or more accurately the SoC variant combining ARM cores with ...
    by Published on 08-28-2014 05:01 AM
    1. Categories:
    2. Semiconductor Manufacturers,
    3. TSMC
    content/attachments/11920-tsmc3.jpg

    For several years now, TSMC has run increasingly sophisticated IP validation. Ramping a new process as a foundry requires a number of things to all come together almost simultaneously: the process, of course, and some designs to run and start to ...
    by Published on 08-27-2014 09:30 PM
    1. Categories:
    2. FPGA,
    3. Xilinx
    content/attachments/11924-alt.jpg

    Coke with no ice. You see I am not cheap, or even frugal but a good steward. One of the things that I hate the most is waste. You know lights on in every room, door open during winter and driving 25 miles to save a dollar ...
    by Published on 08-27-2014 02:00 PM
    1. Categories:
    2. Semiconductor Design
    content/attachments/11874-clip_image002.gif

    Metal fill requirements for inductors are now a fact of life. Fill has long been seen as detrimental to device performance due to parasitic capacitance. The necessity of fill arises from the need to ensure planarization of dielectric layers by using chemical mechanical polishing. Without adequate fill, areas of the chip can ...
    by Published on 08-27-2014 05:01 AM
    1. Categories:
    2. Semiconductor Manufacturers
    content/attachments/11909-wiced1.jpg

    One of the perks of blogging here is being able to get a press invitation to lots of events, often in interesting locations I never even knew existed. Tonight it was a Broadcom event in SPUR here in San Francisco. The ...
    by Published on 08-26-2014 06:00 PM
    1. Categories:
    2. Semiconductor Design
    content/attachments/11901-transfer1.jpg

    Most analog designers are aware of loops stability. In most cases, stability is understood as AC stability, the goal is ensuring enough phase (gain) margin so as to avoid the loop to enter oscillation. But prior to studying AC stability, DC stability should be questioned. What is that DC stability only few people think of?
    ...
    by Published on 08-26-2014 10:00 AM
    1. Categories:
    2. Semiconductor IP,
    3. ARM
    content/attachments/11899-arm-cortex-m0plus-chip-diagram.jpg

    Behind much of the success of ARM architecture is a scalable software model, where in theory the same code runs on the smallest member of the family to the largest. In practice, there are profiles, and a variety of hardware execution units, and resource ...
    by Published on 08-25-2014 05:08 PM
    1. Categories:
    2. Semiconductor Design,
    3. Mentor
    content/attachments/11900-mentor_logo.png

    Mentor's results came out last week. They were good. Wally opened the call:
    Thanks. Once again results for Mentor Graphics in the quarter exceeded our guidance. Revenue of $260.2 million and non-GAAP earnings per share of $0.23, were ahead of our guidance of $250 million and $0.15
    ...

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